Index: trunk/WB2ALTDDR3/dram_wb.v
===================================================================
--- trunk/WB2ALTDDR3/dram_wb.v	(revision 17)
+++ trunk/WB2ALTDDR3/dram_wb.v	(revision 22)
@@ -22,6 +22,6 @@
 module dram_wb(
    input             clk200,
-   input             rup,
-   input             rdn,
+//   input             rup,
+//   input             rdn,
 
    input             wb_clk_i,
@@ -64,7 +64,8 @@
 );
 
+wire app_af_afull;
 wire [127:0] rd_data_fifo_out;
 reg  [ 23:0] rd_addr_cache;
-wire [127:0] wr_dout;
+wire [ 71:0] wr_dout;
 wire [ 31:0] cmd_out;
 reg          wb_stb_i_d;
@@ -78,29 +79,36 @@
 //wire [13:0] seriesterminationcontrol;
 
-dram dram_ctrl(
+dram #
+     (
+     //synthesis traslate off
+     .SIM_ONLY              (1)
+     //synthesis traslate on
+      )
+    dram_ctrl(
     .sys_clk(clk200),
     .sys_rst_n(sysrst),  // Resets all
     .phy_init_done(phy_init_done),
+    
+    .app_af_cmd({2'b00,!cmd_out[31]}), //command for the controller 000:write 001:read
+    .app_af_addr(cmd_out[30:0]),
+    .app_af_wren(push_tran), //write enable for address fifo
+    .app_wdf_wren(cmd_out[31] & push_tran), // write enable for write data fifo
+    .app_wdf_data({wr_dout[63:0],wr_dout[63:0]}),
     .app_wdf_mask_data(mask_data),
-    .app_af_addr(cmd_out[31:1]),
+    
     .rd_data_valid(rd_data_valid),
     .rd_data_fifo_out(rd_data_fifo_out),    
-    .app_wdf_data(wr_dout[127:0]),
-	 
-	 // in dubbio
-	 .app_wdf_wren(1'b1),
-         .app_af_wren(1'b1),
-	 .app_af_afull(),
-	 .app_wdf_afull(),
-         .app_af_cmd(),
-	 .clk0_tb(),
-	 .idly_clk_200(clk200),
-	 .rst0_tb(ddr3_reset),
-    
-    .ddr2_dqs(ddr3_dqs),
-    .ddr2_dqs_n(ddr3_dqs_n),
+    
+    .clk0_tb(ddr_clk),
+    .rst0_tb(ddr3_reset),	 
+    .app_af_afull(app_af_afull),
+    .app_wdf_afull(),
+    .idly_clk_200(clk200),
+
     .ddr2_ck(ddr3_ck),
     .ddr2_ck_n(ddr3_ck_n),
     .ddr2_dq(ddr3_dq),
+    .ddr2_dqs(ddr3_dqs),
+    .ddr2_dqs_n(ddr3_dqs_n),
     .ddr2_ras_n(ddr3_ras_n),
     .ddr2_cas_n(ddr3_cas_n),
@@ -112,16 +120,7 @@
     .ddr2_a(ddr3_a),
     .ddr2_dm(ddr3_dm)
-//               |
-//non sostituiti\|/
-//               V 
-//    .phy_clk(ddr_clk),         // User clock
-//    .local_ready(dram_ready),
-//    .local_burstbegin(push_tran),
-//    .local_read_req(!cmd_out[31] && push_tran),
-//    .local_write_req(cmd_out[31] && push_tran),
-//    .local_wdata({wr_dout[63:0],wr_dout[63:0],wr_dout[63:0],wr_dout[63:0]}),
-//    .local_size(3'b001)
-    
 );
+
+assign dram_ready = phy_init_done && !app_af_afull;
 
 /* comment by sal
@@ -179,5 +178,5 @@
 */
 
-assign ddr_rst=!phy_init_done;
+assign ddr_rst=!phy_init_done; 
 
 /*oct_alt_oct_power_f4c oct
@@ -190,9 +189,7 @@
 
 always @( * )
-   case(cmd_out[1:0])
-      2'b00:mask_data<={24'h000000,wr_dout[71:64]};
-      2'b01:mask_data<={16'h0000,wr_dout[71:64],8'h00};
-      2'b10:mask_data<={8'h00,wr_dout[71:64],16'h0000};
-      2'b11:mask_data<={wr_dout[71:64],24'h000000};
+   case(cmd_out[0])
+      1'b0:mask_data<={8'h00,wr_dout[71:64]};
+      1'b1:mask_data<={wr_dout[71:64],8'h00};
    endcase
 
@@ -304,14 +301,15 @@
 
 always @( * )
-   case(wb_adr_i[4:3])
-      2'b00:wb_dat_o<=rd_data_fifo_out_d[63:0];
-      2'b01:wb_dat_o<=rd_data_fifo_out_d[127:64];
-      2'b10:wb_dat_o<=rd_data_fifo_out_d[191:128];
-      2'b11:wb_dat_o<=rd_data_fifo_out_d[255:192];
+   case(wb_adr_i[3])
+      1'b0:wb_dat_o<=rd_data_fifo_out_d[63:0];
+      1'b1:wb_dat_o<=rd_data_fifo_out_d[127:64];
    endcase
 
 always @(posedge wb_clk_i or posedge wb_rst_i)
    if(wb_rst_i)
-      rd_addr_cache<=24'hFFFFFF;
+      begin
+	//written<=0;
+      	rd_addr_cache<=24'hFFFFFF;
+      end
    else
    begin