Index: trunk/sim/tb_top.v
===================================================================
--- trunk/sim/tb_top.v	(revision 17)
+++ trunk/sim/tb_top.v	(revision 22)
@@ -14,4 +14,9 @@
    localparam real TCYC_200           = 5.0;
    parameter RST_ACT_LOW           = 1;      // =1 for active low reset, =0 for active high
+   localparam real TPROP_DQS          = 0.01;  // Delay for DQS signal during Write Operation
+   localparam real TPROP_DQS_RD       = 0.01;  // Delay for DQS signal during Read Operation
+   localparam real TPROP_PCB_CTRL     = 0.01;  // Delay for Address and Ctrl signals
+   localparam real TPROP_PCB_DATA     = 0.01;  // Delay for data signal during Write operation
+   localparam real TPROP_PCB_DATA_RD  = 0.01;  // Delay for data signal during Read operation
 
 
@@ -32,14 +37,31 @@
    wire [DQS_WIDTH-1:0]         ddr2_dqs_n_sdram;
    wire [7:0]                   ddr2_dm_sdram;
-   wire      		                 ddr2_clk_sdram;
-   wire           		            ddr2_clk_n_sdram;
-   wire [12:0]          		      ddr2_address_sdram;
-   wire [1:0]         		        ddr2_ba_sdram;
-   wire                         ddr2_ras_n_sdram;
-   wire                         ddr2_cas_n_sdram;
-   wire                         ddr2_we_n_sdram;
-   wire [CS_WIDTH-1:0]          ddr2_cs_n_sdram;
-   wire 			ddr2_cke_sdram;
-   wire [ODT_WIDTH-1:0]         ddr2_odt_sdram;
+   reg  [7:0]           	ddr2_dm_sdram_tmp;
+   reg      		        ddr2_clk_sdram;
+   reg           		ddr2_clk_n_sdram;
+   reg  [12:0]          	ddr2_address_sdram;
+   reg  [1:0]         		ddr2_ba_sdram;
+   reg                          ddr2_ras_n_sdram;
+   reg                          ddr2_cas_n_sdram;
+   reg                          ddr2_we_n_sdram;
+   reg [CS_WIDTH-1:0]           ddr2_cs_n_sdram;
+   reg 			        ddr2_cke_sdram;
+   reg [ODT_WIDTH-1:0]          ddr2_odt_sdram;
+
+   wire [DQ_WIDTH-1:0]          ddr2_dq_fpga;
+   wire [DQS_WIDTH-1:0]         ddr2_dqs_fpga;
+   wire [DQS_WIDTH-1:0]         ddr2_dqs_n_fpga;
+   wire [7:0]          		ddr2_dm_fpga;
+   wire 		        ddr2_clk_fpga;
+   wire          		ddr2_clk_n_fpga;
+   wire [12:0]         		ddr2_address_fpga;
+   wire [1:0]        		ddr2_ba_fpga;
+   wire                         ddr2_ras_n_fpga;
+   wire                         ddr2_cas_n_fpga;
+   wire                         ddr2_we_n_fpga;
+   wire [CS_WIDTH-1:0]          ddr2_cs_n_fpga;
+   wire          		ddr2_cke_fpga;
+   wire [ODT_WIDTH-1:0]         ddr2_odt_fpga;
+
 
    wire 			 stx;
@@ -57,6 +79,6 @@
           
     // Create VCD trace file
-         $dumpfile("trace.vcd");
-         $dumpvars();
+    //     $dumpfile("trace.vcd");
+    //     $dumpvars();
                        
     // Run the simulation
@@ -65,5 +87,5 @@
     //     #1000
     //     sys_reset <= 1'b0;
-         #100000
+         #700_000 
          $display("INFO: TBENCH: Completed simulation!");
          $finish;
@@ -109,18 +131,18 @@
 
    // ddr3 memory interface
-   .ddr3_dq (ddr2_dq_sdram),            
-   .ddr3_dqs (ddr2_dqs_n_sdram),
-   .ddr3_dqs_n (ddr2_dqs_n_sdram),
-   .ddr3_ck (ddr2_clk_sdram),
-   .ddr3_ck_n (ddr2_clk_n_sdram),
-   .ddr3_a (ddr2_address_sdram),
-   .ddr3_ba (ddr2_ba_sdram), //FIXME
-   .ddr3_ras_n (ddr2_ras_n_sdram),
-   .ddr3_cas_n (ddr2_cas_n_sdram),
-   .ddr3_we_n (ddr2_we_n_sdram),
-   .ddr3_cs_n (ddr2_cs_n_sdram),
-   .ddr3_odt (ddr2_odt_sdram),
-   .ddr3_ce (ddr2_cke_sdram),
-   .ddr3_dm (ddr2_dm_sdram),
+   .ddr3_dq (ddr2_dq_fpga),            
+   .ddr3_dqs (ddr2_dqs_fpga),
+   .ddr3_dqs_n (ddr2_dqs_n_fpga),
+   .ddr3_ck (ddr2_clk_fpga),
+   .ddr3_ck_n (ddr2_clk_n_fpga),
+   .ddr3_a (ddr2_address_fpga),
+   .ddr3_ba (ddr2_ba_fpga), //FIXME
+   .ddr3_ras_n (ddr2_ras_n_fpga),
+   .ddr3_cas_n (ddr2_cas_n_fpga),
+   .ddr3_we_n (ddr2_we_n_fpga),
+   .ddr3_cs_n (ddr2_cs_n_fpga),
+   .ddr3_odt (ddr2_odt_fpga),
+   .ddr3_ce (ddr2_cke_fpga),
+   .ddr3_dm (ddr2_dm_fpga),
 
    // Console interface
@@ -156,4 +178,71 @@
    .flash_rst(flash_rst)
 );
+
+//DDR2 model
+//
+
+ always @( * ) begin
+    ddr2_clk_sdram        <=  #(TPROP_PCB_CTRL) ddr2_clk_fpga;
+    ddr2_clk_n_sdram      <=  #(TPROP_PCB_CTRL) ddr2_clk_n_fpga;
+    ddr2_address_sdram    <=  #(TPROP_PCB_CTRL) ddr2_address_fpga;
+    ddr2_ba_sdram         <=  #(TPROP_PCB_CTRL) ddr2_ba_fpga;
+    ddr2_ras_n_sdram      <=  #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
+    ddr2_cas_n_sdram      <=  #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
+    ddr2_we_n_sdram       <=  #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
+    ddr2_cs_n_sdram       <=  #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
+    ddr2_cke_sdram        <=  #(TPROP_PCB_CTRL) ddr2_cke_fpga;
+    ddr2_odt_sdram        <=  #(TPROP_PCB_CTRL) ddr2_odt_fpga;
+    ddr2_dm_sdram_tmp     <=  #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
+  end
+
+assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
+
+genvar dqwd;
+  generate
+    for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
+      WireDelay #
+       (
+        .Delay_g     (TPROP_PCB_DATA),
+        .Delay_rd    (TPROP_PCB_DATA_RD)
+       )
+      u_delay_dq
+       (
+        .A           (ddr2_dq_fpga[dqwd]),
+        .B           (ddr2_dq_sdram[dqwd]),
+        .reset       (sys_rst_n)
+       );
+    end
+  endgenerate
+
+
+ genvar dqswd;
+  generate
+    for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
+      WireDelay #
+       (
+        .Delay_g     (TPROP_DQS),
+        .Delay_rd    (TPROP_DQS_RD)
+       )
+      u_delay_dqs
+       (
+        .A           (ddr2_dqs_fpga[dqswd]),
+        .B           (ddr2_dqs_sdram[dqswd]),
+        .reset       (sys_rst_n)
+       );
+
+      WireDelay #
+       (
+        .Delay_g     (TPROP_DQS),
+        .Delay_rd    (TPROP_DQS_RD)
+       )
+      u_delay_dqs_n
+       (
+        .A           (ddr2_dqs_n_fpga[dqswd]),
+        .B           (ddr2_dqs_n_sdram[dqswd]),
+        .reset       (sys_rst_n)
+       );
+    end
+  endgenerate
+
            // if the data width is multiple of 16
               //for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs
