Index: trunk/sim/sim_tb_top.v =================================================================== --- trunk/sim/sim_tb_top.v (revision 10) +++ trunk/sim/sim_tb_top.v (revision 22) @@ -289,5 +289,5 @@ .CS_WIDTH (CS_WIDTH), .CS_BITS (CS_BITS), - .DM_WIDTH (DM_WIDTH), + .DM_WIDTH (DM_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQ_PER_DQS (DQ_PER_DQS), @@ -318,6 +318,6 @@ .SIM_ONLY (SIM_ONLY), .RST_ACT_LOW (RST_ACT_LOW), - .CLK_TYPE (CLK_TYPE), - .DLL_FREQ_MODE (DLL_FREQ_MODE), + .CLK_TYPE (CLK_TYPE), + .DLL_FREQ_MODE (DLL_FREQ_MODE), .CLK_PERIOD (CLK_PERIOD) ) @@ -341,5 +341,5 @@ .ddr2_ba (ddr2_ba_fpga), .ddr2_a (ddr2_address_fpga), - .error (error), + //.error (error), Index: trunk/sim/simula.do =================================================================== --- trunk/sim/simula.do (revision 17) +++ trunk/sim/simula.do (revision 22) @@ -45,4 +45,6 @@ #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl +add wave sim:/tb_top/W1_inst/dram_wb_inst/* +#exit pause onerror {resume} Index: trunk/sim/tb_top.v =================================================================== --- trunk/sim/tb_top.v (revision 17) +++ trunk/sim/tb_top.v (revision 22) @@ -14,4 +14,9 @@ localparam real TCYC_200 = 5.0; parameter RST_ACT_LOW = 1; // =1 for active low reset, =0 for active high + localparam real TPROP_DQS = 0.01; // Delay for DQS signal during Write Operation + localparam real TPROP_DQS_RD = 0.01; // Delay for DQS signal during Read Operation + localparam real TPROP_PCB_CTRL = 0.01; // Delay for Address and Ctrl signals + localparam real TPROP_PCB_DATA = 0.01; // Delay for data signal during Write operation + localparam real TPROP_PCB_DATA_RD = 0.01; // Delay for data signal during Read operation @@ -32,14 +37,31 @@ wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram; wire [7:0] ddr2_dm_sdram; - wire ddr2_clk_sdram; - wire ddr2_clk_n_sdram; - wire [12:0] ddr2_address_sdram; - wire [1:0] ddr2_ba_sdram; - wire ddr2_ras_n_sdram; - wire ddr2_cas_n_sdram; - wire ddr2_we_n_sdram; - wire [CS_WIDTH-1:0] ddr2_cs_n_sdram; - wire ddr2_cke_sdram; - wire [ODT_WIDTH-1:0] ddr2_odt_sdram; + reg [7:0] ddr2_dm_sdram_tmp; + reg ddr2_clk_sdram; + reg ddr2_clk_n_sdram; + reg [12:0] ddr2_address_sdram; + reg [1:0] ddr2_ba_sdram; + reg ddr2_ras_n_sdram; + reg ddr2_cas_n_sdram; + reg ddr2_we_n_sdram; + reg [CS_WIDTH-1:0] ddr2_cs_n_sdram; + reg ddr2_cke_sdram; + reg [ODT_WIDTH-1:0] ddr2_odt_sdram; + + wire [DQ_WIDTH-1:0] ddr2_dq_fpga; + wire [DQS_WIDTH-1:0] ddr2_dqs_fpga; + wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga; + wire [7:0] ddr2_dm_fpga; + wire ddr2_clk_fpga; + wire ddr2_clk_n_fpga; + wire [12:0] ddr2_address_fpga; + wire [1:0] ddr2_ba_fpga; + wire ddr2_ras_n_fpga; + wire ddr2_cas_n_fpga; + wire ddr2_we_n_fpga; + wire [CS_WIDTH-1:0] ddr2_cs_n_fpga; + wire ddr2_cke_fpga; + wire [ODT_WIDTH-1:0] ddr2_odt_fpga; + wire stx; @@ -57,6 +79,6 @@ // Create VCD trace file - $dumpfile("trace.vcd"); - $dumpvars(); + // $dumpfile("trace.vcd"); + // $dumpvars(); // Run the simulation @@ -65,5 +87,5 @@ // #1000 // sys_reset <= 1'b0; - #100000 + #700_000 $display("INFO: TBENCH: Completed simulation!"); $finish; @@ -109,18 +131,18 @@ // ddr3 memory interface - .ddr3_dq (ddr2_dq_sdram), - .ddr3_dqs (ddr2_dqs_n_sdram), - .ddr3_dqs_n (ddr2_dqs_n_sdram), - .ddr3_ck (ddr2_clk_sdram), - .ddr3_ck_n (ddr2_clk_n_sdram), - .ddr3_a (ddr2_address_sdram), - .ddr3_ba (ddr2_ba_sdram), //FIXME - .ddr3_ras_n (ddr2_ras_n_sdram), - .ddr3_cas_n (ddr2_cas_n_sdram), - .ddr3_we_n (ddr2_we_n_sdram), - .ddr3_cs_n (ddr2_cs_n_sdram), - .ddr3_odt (ddr2_odt_sdram), - .ddr3_ce (ddr2_cke_sdram), - .ddr3_dm (ddr2_dm_sdram), + .ddr3_dq (ddr2_dq_fpga), + .ddr3_dqs (ddr2_dqs_fpga), + .ddr3_dqs_n (ddr2_dqs_n_fpga), + .ddr3_ck (ddr2_clk_fpga), + .ddr3_ck_n (ddr2_clk_n_fpga), + .ddr3_a (ddr2_address_fpga), + .ddr3_ba (ddr2_ba_fpga), //FIXME + .ddr3_ras_n (ddr2_ras_n_fpga), + .ddr3_cas_n (ddr2_cas_n_fpga), + .ddr3_we_n (ddr2_we_n_fpga), + .ddr3_cs_n (ddr2_cs_n_fpga), + .ddr3_odt (ddr2_odt_fpga), + .ddr3_ce (ddr2_cke_fpga), + .ddr3_dm (ddr2_dm_fpga), // Console interface @@ -156,4 +178,71 @@ .flash_rst(flash_rst) ); + +//DDR2 model +// + + always @( * ) begin + ddr2_clk_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_fpga; + ddr2_clk_n_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_n_fpga; + ddr2_address_sdram <= #(TPROP_PCB_CTRL) ddr2_address_fpga; + ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga; + ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga; + ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga; + ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga; + ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga; + ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga; + ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga; + ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation + end + +assign ddr2_dm_sdram = ddr2_dm_sdram_tmp; + +genvar dqwd; + generate + for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay + WireDelay # + ( + .Delay_g (TPROP_PCB_DATA), + .Delay_rd (TPROP_PCB_DATA_RD) + ) + u_delay_dq + ( + .A (ddr2_dq_fpga[dqwd]), + .B (ddr2_dq_sdram[dqwd]), + .reset (sys_rst_n) + ); + end + endgenerate + + + genvar dqswd; + generate + for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay + WireDelay # + ( + .Delay_g (TPROP_DQS), + .Delay_rd (TPROP_DQS_RD) + ) + u_delay_dqs + ( + .A (ddr2_dqs_fpga[dqswd]), + .B (ddr2_dqs_sdram[dqswd]), + .reset (sys_rst_n) + ); + + WireDelay # + ( + .Delay_g (TPROP_DQS), + .Delay_rd (TPROP_DQS_RD) + ) + u_delay_dqs_n + ( + .A (ddr2_dqs_n_fpga[dqswd]), + .B (ddr2_dqs_n_sdram[dqswd]), + .reset (sys_rst_n) + ); + end + endgenerate + // if the data width is multiple of 16 //for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs Index: trunk/sim/wiredly.vhd =================================================================== --- trunk/sim/wiredly.vhd (revision 10) +++ (revision ) @@ -1,133 +1,0 @@ ---***************************************************************************** --- DISCLAIMER OF LIABILITY --- --- This file contains proprietary and confidential information of --- Xilinx, Inc. ("Xilinx"), that is distributed under a license --- from Xilinx, and may be used, copied and/or disclosed only --- pursuant to the terms of a valid license agreement with Xilinx. --- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION --- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER --- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT --- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, --- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx --- does not warrant that functions included in the Materials will --- meet the requirements of Licensee, or that the operation of the --- Materials will be uninterrupted or error-free, or that defects --- in the Materials will be corrected. Furthermore, Xilinx does --- not warrant or make any representations regarding use, or the --- results of the use, of the Materials in terms of correctness, --- accuracy, reliability or otherwise. --- --- Xilinx products are not designed or intended to be fail-safe, --- or for use in any application requiring fail-safe performance, --- such as life-support or safety devices or systems, Class III --- medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could --- lead to death, personal injury or severe property or --- environmental damage (individually and collectively, "critical --- applications"). Customer assumes the sole risk and liability --- of any use of Xilinx products in critical applications, --- subject only to applicable laws and regulations governing --- limitations on product liability. --- --- Copyright 2007, 2008 Xilinx, Inc. --- All rights reserved. --- --- This disclaimer and copyright notice must be retained as part --- of this file at all times. ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : 3.6 --- \ \ Application : MIG --- / / Filename : wiredly.vhd --- /___/ /\ Date Last Modified : $Date: 2010/06/29 12:03:42 $ --- \ \ / \ Date Created : Mon Jun 18 2007 --- \___\/\___\ --- --- Device : Virtex-5 --- Design Name : DDR2 --- Description: This module provide --- the definition of a zero ohm component (A, B). --- --- The applications of this component include: --- . Normal operation of a jumper wire (data flowing in both directions) --- --- The component consists of 2 ports: --- . Port A: One side of the pass-through switch --- . Port B: The other side of the pass-through switch - --- The model is sensitive to transactions on all ports. Once a --- transaction is detected, all other transactions are ignored --- for that simulation time (i.e. further transactions in that --- delta time are ignored). --- --- Model Limitations and Restrictions: --- Signals asserted on the ports of the error injector should not have --- transactions occuring in multiple delta times because the model --- is sensitive to transactions on port A, B ONLY ONCE during --- a simulation time. Thus, once fired, a process will --- not refire if there are multiple transactions occuring in delta times. --- This condition may occur in gate level simulations with --- ZERO delays because transactions may occur in multiple delta times. ---***************************************************************************** - -library IEEE; - use IEEE.Std_Logic_1164.all; - -entity WireDelay is - generic ( - Delay_g : time; - Delay_rd : time); - port - (A : inout Std_Logic; - B : inout Std_Logic; - reset : in Std_Logic - ); -end WireDelay; - - -architecture WireDelay_a of WireDelay is - - signal A_r : Std_Logic; - signal B_r : Std_Logic; - signal line_en : Std_Logic; - -begin - - A <= A_r; - B <= B_r; - - ABC0_Lbl: process (reset, A, B) - begin - if (reset = '0') then - line_en <= '0'; - else - if (A /= A_r) then - line_en <= '0'; - elsif (B_r /= B) then - line_en <= '1'; - else - line_en <= line_en; - end if; - end if; - - end process ABC0_Lbl; - - lnenab: process (reset, line_en, A, B) - begin - if (reset = '0') then - A_r <= 'Z'; - B_r <= 'Z'; - elsif (line_en = '1') then - A_r <= TRANSPORT B AFTER Delay_rd; - B_r <= 'Z'; - else - B_r <= TRANSPORT A AFTER Delay_g; - A_r <= 'Z'; - end if; - end process; - -end WireDelay_a; Index: trunk/sim/sim.do =================================================================== --- trunk/sim/sim.do (revision 10) +++ (revision ) @@ -1,125 +1,0 @@ -############################################################################### -## DISCLAIMER OF LIABILITY -## -## This file contains proprietary and confidential information of -## Xilinx, Inc. ("Xilinx"), that is distributed under a license -## from Xilinx, and may be used, copied and/or disclosed only -## pursuant to the terms of a valid license agreement with Xilinx. -## -## XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -## ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -## EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -## LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -## MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -## does not warrant that functions included in the Materials will -## meet the requirements of Licensee, or that the operation of the -## Materials will be uninterrupted or error-free, or that defects -## in the Materials will be corrected. Furthermore, Xilinx does -## not warrant or make any representations regarding use, or the -## results of the use, of the Materials in terms of correctness, -## accuracy, reliability or otherwise. -## -## Xilinx products are not designed or intended to be fail-safe, -## or for use in any application requiring fail-safe performance, -## such as life-support or safety devices or systems, Class III -## medical devices, nuclear facilities, applications related to -## the deployment of airbags, or any other applications that could -## lead to death, personal injury or severe property or -## environmental damage (individually and collectively, "critical -## applications"). Customer assumes the sole risk and liability -## of any use of Xilinx products in critical applications, -## subject only to applicable laws and regulations governing -## limitations on product liability. -## -## Copyright 2007, 2008 Xilinx, Inc. -## All rights reserved. -## -## This disclaimer and copyright notice must be retained as part -## of this file at all times. -############################################################################### -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.6 -## \ \ Application : MIG -## / / Filename : sim.do -## /___/ /\ Date Last Modified : $Date: 2010/06/29 12:03:41 $ -## \ \ / \ Date Created : Mon May 14 2007 -## \___\/\___\ -## -##Device: Virtex-5 -##Purpose: -## Sample sim .do file to compile and simulate memory interface -## design and run the simulation for specified period of time. Display the -## waveforms that are listed with "add wave" command. -## Assumptions: -## - Simulation takes place in \sim folder of MIG output directory -##Reference: -##Revision History: -############################################################################### -vlib work - -#Map the required libraries here.# - -#Compile all modules# -vlog ../rtl/ddr2_chipscope* -vlog ../rtl/* -#Compile files in sim folder (excluding model parameter file)# -#$XILINX variable must be set -vlog $env(XILINX)/verilog/src/glbl.v -vlog ../sim/*.v - -#Pass the parameters for memory model parameter file# -vlog +incdir+. +define+x512Mb +define+sg37E +define+x16 ddr2_model.v - -#Load the design. Use required libraries.# -vsim -t ps -novopt +notimingchecks -L unisims_ver work.sim_tb_top glbl - -onerror {resume} -#Log all the objects in design. These will appear in .wlf file# -log -r /* -#View sim_tb_top signals in waveform# -add wave sim:/sim_tb_top/* - -#Change radix to Hexadecimal# -radix hex -#Supress Numeric Std package and Arith package warnings.# -#For VHDL designs we get some warnings due to unknown values on some signals at startup# -# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0# -#We may also get some Arithmetic packeage warnings because of unknown values on# -#some of the signals that are used in an Arithmetic operation.# -#In order to suppress these warnings, we use following two commands# -set NumericStdNoWarnings 1 -set StdArithNoWarnings 1 - -#Choose simulation run time by inserting a breakpoint and then run for specified # -#period. For more details, refer to Simulation Guide section of MIG user guide (UG086).# -when {/sim_tb_top/phy_init_done = 1} { -if {[when -label a_100] == ""} { -when -label a_100 { $now = 50 us } { -nowhen a_100 -report simulator control -report simulator state -if {[examine /sim_tb_top/error] == 0} { -echo "TEST PASSED" -stop -} -if {[examine /sim_tb_top/error] != 0} { -echo "TEST FAILED: DATA ERROR" -stop -} -} -} -} - -#In case calibration fails to complete, choose the run time and then stop# -when {$now = @500 us and /sim_tb_top/phy_init_done != 1} { -echo "TEST FAILED: CALIBRATION DID NOT COMPLETE" -stop -} - -echo "NOTE: Initial 200us power on period is skipped for simulation. - Change SIM_ONLY parameter in sim_tb_top file to activate this." - -run -all -stop