Index: trunk/WB2ALTDDR3/dram_wb.v
===================================================================
--- trunk/WB2ALTDDR3/dram_wb.v	(revision 22)
+++ trunk/WB2ALTDDR3/dram_wb.v	(revision 23)
@@ -40,19 +40,19 @@
    input             wb_cab_i, 
 
-   inout      [63:0] ddr3_dq,
-   inout      [ 7:0] ddr3_dqs,
-   inout      [ 7:0] ddr3_dqs_n,
-   inout             ddr3_ck,
-   inout             ddr3_ck_n,
+   inout      [63:0] ddr2_dq,
+   inout      [ 7:0] ddr2_dqs,
+   inout      [ 7:0] ddr2_dqs_n,
+   inout             ddr2_ck,
+   inout             ddr2_ck_n,
    //output            ddr3_reset,
-   output     [12:0] ddr3_a,
-   output     [ 1:0] ddr3_ba,
-   output            ddr3_ras_n,
-   output            ddr3_cas_n,
-   output            ddr3_we_n,
-   output            ddr3_cs_n,
-   output            ddr3_odt,
-   output            ddr3_ce,
-   output     [ 7:0] ddr3_dm,
+   output     [12:0] ddr2_a,
+   output     [ 1:0] ddr2_ba,
+   output            ddr2_ras_n,
+   output            ddr2_cas_n,
+   output            ddr2_we_n,
+   output            ddr2_cs_n,
+   output            ddr2_odt,
+   output            ddr2_ce,
+   output     [ 7:0] ddr2_dm,
 
    output            phy_init_done,
@@ -74,5 +74,6 @@
 wire dram_ready;
 wire fifo_empty;
-reg       push_tran;
+reg  push_tran_wdf;
+reg  push_tran;
 
 //wire [13:0] parallelterminationcontrol;
@@ -85,5 +86,6 @@
      //synthesis traslate on
       )
-    dram_ctrl(
+    // cmd_out[31] è il WE, CMD_OUT[30:0] corrisponde ad wb_addr[33:3]
+     dram_ctrl(
     .sys_clk(clk200),
     .sys_rst_n(sysrst),  // Resets all
@@ -93,5 +95,5 @@
     .app_af_addr(cmd_out[30:0]),
     .app_af_wren(push_tran), //write enable for address fifo
-    .app_wdf_wren(cmd_out[31] & push_tran), // write enable for write data fifo
+    .app_wdf_wren(push_tran_wdf), // write enable for write data fifo
     .app_wdf_data({wr_dout[63:0],wr_dout[63:0]}),
     .app_wdf_mask_data(mask_data),
@@ -106,18 +108,18 @@
     .idly_clk_200(clk200),
 
-    .ddr2_ck(ddr3_ck),
-    .ddr2_ck_n(ddr3_ck_n),
-    .ddr2_dq(ddr3_dq),
-    .ddr2_dqs(ddr3_dqs),
-    .ddr2_dqs_n(ddr3_dqs_n),
-    .ddr2_ras_n(ddr3_ras_n),
-    .ddr2_cas_n(ddr3_cas_n),
-    .ddr2_odt(ddr3_odt),
-    .ddr2_cs_n(ddr3_cs_n),
-    .ddr2_cke(ddr3_ce),
-    .ddr2_we_n(ddr3_we_n),
-    .ddr2_ba(ddr3_ba),
-    .ddr2_a(ddr3_a),
-    .ddr2_dm(ddr3_dm)
+    .ddr2_ck(ddr2_ck),
+    .ddr2_ck_n(ddr2_ck_n),
+    .ddr2_dq(ddr2_dq),
+    .ddr2_dqs(ddr2_dqs),
+    .ddr2_dqs_n(ddr2_dqs_n),
+    .ddr2_ras_n(ddr2_ras_n),
+    .ddr2_cas_n(ddr2_cas_n),
+    .ddr2_odt(ddr2_odt),
+    .ddr2_cs_n(ddr2_cs_n),
+    .ddr2_cke(ddr2_ce),
+    .ddr2_we_n(ddr2_we_n),
+    .ddr2_ba(ddr2_ba),
+    .ddr2_a(ddr2_a),
+    .ddr2_dm(ddr2_dm)
 );
 
@@ -189,8 +191,15 @@
 
 always @( * )
-   case(cmd_out[0])
-      1'b0:mask_data<={8'h00,wr_dout[71:64]};
-      1'b1:mask_data<={wr_dout[71:64],8'h00};
+     case(push_tran & cmd_out[31])
+      1'b1:mask_data<=16'hffff;
+      1'b0:mask_data<={wr_dout[71:64],8'h00};
+      //1'b1:mask_data<={wr_dout[71:64] ^ 8'hff,8'hff}; FIXME il sel e' in logica negata
    endcase
+
+//always @( * )
+//   case(cmd_out[0])
+//      1'b0:mask_data<={8'h00,wr_dout[71:64]};
+//      1'b1:mask_data<={wr_dout[71:64],8'h00};
+//   endcase
 
 //wire [254:0] trig0;
@@ -217,7 +226,7 @@
 reg fifo_full_d;
 reg written;
-reg       fifo_read;
-
-dram_fifo fifo(
+reg fifo_read;
+
+dram_fifo_fall fifo(
    .rst(ddr_rst),
    .wr_clk(wb_clk_i),
@@ -235,4 +244,5 @@
 `define DDR_WRITE_1 3'b001
 `define DDR_WRITE_2 3'b010
+`define DDR_WRITE_3 3'b110
 `define DDR_READ_1  3'b011
 `define DDR_READ_2  3'b100
@@ -242,4 +252,5 @@
 reg wb_ack_d1;
 
+//FIXME si perde il primo comando di scrittura 
 always @(posedge ddr_clk or posedge ddr_rst)
    if(ddr_rst)
@@ -247,4 +258,5 @@
          ddr_state<=`DDR_IDLE;
          fifo_read<=0;
+         push_tran_wdf<=0;
          push_tran<=0;
          rd_data_valid_stb<=0;
@@ -255,21 +267,31 @@
             if(!fifo_empty && dram_ready)
                begin
-                  push_tran<=1;
                   if(cmd_out[31])
                      begin
+                        push_tran_wdf<=1;
                         ddr_state<=`DDR_WRITE_1;
-                        fifo_read<=1;
                      end
                   else
+                     begin
+		     push_tran<=1;
                      ddr_state<=`DDR_READ_1;
-               end
+                  end
+		end
          `DDR_WRITE_1:
             begin
-               push_tran<=0;
-               fifo_read<=0;
+               fifo_read<=1;
+               push_tran_wdf<=1;
+               push_tran<=1;
                ddr_state<=`DDR_WRITE_2; // Protect against FIFO empty signal latency
             end
          `DDR_WRITE_2:
-            ddr_state<=`DDR_IDLE;
+               begin
+		fifo_read<=0;
+                push_tran_wdf<=0;
+                push_tran<=0;
+                ddr_state<=`DDR_WRITE_3;
+	       end
+         `DDR_WRITE_3:
+               ddr_state<=`DDR_IDLE;
          `DDR_READ_1:
             begin
@@ -297,11 +319,14 @@
 reg rd_data_valid_stb_d3;
 reg rd_data_valid_stb_d4;
-reg [127:0] rd_data_fifo_out_d;
+reg [127:0] rd_data_fifo_out_dH;
+reg [127:0] rd_data_fifo_out_dL;
 reg wb_ack_d;
 
 always @( * )
-   case(wb_adr_i[3])
-      1'b0:wb_dat_o<=rd_data_fifo_out_d[63:0];
-      1'b1:wb_dat_o<=rd_data_fifo_out_d[127:64];
+   case(wb_adr_i[4:3])
+      2'b00:wb_dat_o<=rd_data_fifo_out_dL[63:0];
+      2'b01:wb_dat_o<=rd_data_fifo_out_dL[127:64];
+      2'b10:wb_dat_o<=rd_data_fifo_out_dH[63:0];
+      2'b11:wb_dat_o<=rd_data_fifo_out_dH[127:64];
    endcase
 
@@ -340,6 +365,10 @@
       wb_ack_d1<=wb_ack_d;
       if(rd_data_valid)
-         rd_data_fifo_out_d<=rd_data_fifo_out;
+         rd_data_fifo_out_dH<=rd_data_fifo_out;
+      if(rd_data_valid && !rd_data_valid_stb)
+         rd_data_fifo_out_dL<=rd_data_fifo_out;
+	
    end
     
 endmodule
+