Index: trunk/sim/flash.v
===================================================================
--- trunk/sim/flash.v	(revision 21)
+++ trunk/sim/flash.v	(revision 26)
@@ -42,17 +42,22 @@
     $readmemh(memfilename, mem);
     $display("INFO: MEMH %m: Memory initialization completed");
+    //for(i=0; i<=1023; i=i+1) $display("mem_i = %x",mem[i]) ;
   end
 `endif
 
 assign flash_data = !flash_oen ? data :16'hzzzz;
- 
 
 always @(posedge flash_clk) begin
     // Read cycle
  if (!flash_oen & flash_wen) 
-		data <= mem[flash_addr];
+        begin
+                //$display("INFO: flash: read from address %x data %x",flash_addr, mem[flash_addr]);
+        	data <= mem[flash_addr];
+	end
     else // Write cycle
-      if (flash_oen & !flash_wen) mem[flash_addr] <= flash_data;
-end
+      if (flash_oen & !flash_wen) 
+		$display("INFO: flash: write to address %x data %x (now disabled)",flash_addr,flash_data);
+                //mem[flash_addr] <= flash_data; FIXME: errouneous spourious writes in flash
+      end
 endmodule
    
Index: trunk/sim/simula.do
===================================================================
--- trunk/sim/simula.do	(revision 22)
+++ trunk/sim/simula.do	(revision 26)
@@ -1,4 +1,7 @@
 #start with: vsim -c -do simula.do
 
+set DEFINE +define+DEBUG+FPGA_SYN
+#+FPGA_NEW_IRF
+set INCLUDEDIR +incdir+../T1-common/include/
 vlib work
 
@@ -7,24 +10,24 @@
 #Compile all modules#
 
-vlog +incdir+../T1-common/include/ ../T1-common/common/*.v
-vlog +incdir+../T1-common/include/ ../Top/*.v
-vlog +incdir+../OC-UART +incdir+../T1-common/include/ ../OC-UART/*.v
-vlog +incdir+../T1-common/include/ ../NOR-flash/*.v
-vlog +incdir+../T1-common/include/ ../os2wb/*.v
-vlog +incdir+../T1-common/include/ ../T1-common/m1/*.V
-vlog +define+FPGA_SYN +incdir+../T1-common/include/ ../T1-common/srams/*.v
-vlog +incdir+../T1-common/include/ ../T1-common/u1/*.V
-vlog +incdir+../T1-common/include/ ../T1-FPU/*.v
-vlog +incdir+../T1-common/include/ +incdir+../WB ../WB/*.v
-vlog +incdir+../T1-common/include/ ../WB2ALTDDR3/*.v
-vlog +incdir+../T1-common/include/ ../Xilinx/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/exu/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/ffu/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/ifu/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/lsu/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/mul/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/rtl/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/spu/*.v
-vlog +incdir+../T1-common/include/ ../T1-CPU/tlu/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-common/common/*.v
+vlog  $DEFINE $INCLUDEDIR  ../Top/*.v
+vlog  $DEFINE +incdir+../OC-UART $INCLUDEDIR ../OC-UART/*.v
+vlog  $DEFINE $INCLUDEDIR ../NOR-flash/*.v
+vlog  $DEFINE $INCLUDEDIR ../os2wb/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-common/m1/*.V
+vlog  $DEFINE $INCLUDEDIR ../T1-common/srams/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-common/u1/*.V
+vlog  $DEFINE $INCLUDEDIR/ ../T1-FPU/*.v
+vlog  $DEFINE $INCLUDEDIR +incdir+../WB ../WB/*.v
+vlog  $DEFINE $INCLUDEDIR ../WB2ALTDDR3/*.v
+vlog  $DEFINE $INCLUDEDIR ../Xilinx/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/exu/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/ffu/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/ifu/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/lsu/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/mul/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/rtl/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/spu/*.v
+vlog  $DEFINE $INCLUDEDIR ../T1-CPU/tlu/*.v
 
 #Compile files in sim folder (excluding model parameter file)#