source: HDLQ/Library/Contents.txt @ 1

Library of QCA verilog modules with clock zones and faut injection capability

different versions with or without bidirectional capability, with or without clock status

mymodule(inputs, outputs, status, fault)

- input, outputs: I/O of the module
- status: clock status of the module -> 00=relax,01=switch, 10=hold, 11=release
- fault: fault injection input(s) selects between fault free module or one of its possible faulty versions

modules: crosswire, fanout, majority voter, inverter, L shaped wire, straight wire

note fanout is:
A
|-C
B

---------------------------------------------------------------
files with only fault injection

crosswire.v
Fanout.v        
MajorityVoter.v
Inverter.v      

---------------------------------------------------------------
files with fault injection and clock 

Crosswire4.v
FanoutA4.v (input A)  
FanoutC4.v: (input C)
MajorityVoter_4.v
Inverter_4.v
LShapedWire4.v
Wire4.v

---------------------------------------------------------------
files with fault injection clock and bidirectionality

Crosswirebi4.v
Fanoutbi4.v:
MajorityVoterBI2.v
MajorityVoterBI4.v
MajorityVoterBI6.v
Inverter_bi4.v
LShapedWire_bi4.v
wirebi4.v